FPGA’s consists of an array of programmable logic blocks of potentially different types including general logic, memory and multiplier blocks surrounded by programmable routing fabric that allows blocks to be programmable interconnect. The array is surrounded by programmable I/O blocks that connect chip to outside world. It is a common practice in FPGA architecture research, to employ an empirical approach to study and explore different design approach called as architecture to know the effect of area-efficiency, speed and power of application/algorithm under test.
There are three common types of architectural abstractions:
- Programmable Architetcure (Gpp, ASIP and DSP)
- Reconfigurable Architetcure (FPGA's) and
- Application specific architecture(ASIC)
Reconfigurable computing is concern with decomposing application into spatially parallel, tilled, application specific pipelines whereas traditional general purpose interprets a linear sequence of instruction with pipelining and other forums of spatial parallelism hidden with the microarchitecture of processor. Reconfigurable Architectures are used for multiple purposes and for wide application domain includes:
FPGA’s are commonly used for functional verification prior to ASIC manufacturing.
As an alternative to develop Application Specific hardware for compute-intensive algorithms-
High performance computing:
To accelerate compute-intensive tasks in a conventional computer systems. The reconfigurable architecture is either placed inside processor data paths or directly on the processor front side bus both fined grained and course grained architectures are candidate of this category.
Advantages of FPGA Prototyping:
- Rapid Prototyping enables less time to market compare to ASIC design
- Allows to validate mathematical aspects of system and electronic hardware design simultaneously
- Cheap and higher return on investment
- High degree of parallelism, more flexibility and easy to reconfigure according to demand
Disadvantages of FPGA Prototyping:
- More power requirement
- Performance figure is based on quality of CAD tools and depth of CAD flow
- Low level of flexibility compared to GPP, ASIP and DSP’s
Following figures explain different ways of architecture design
When application demands for minimum resources but can permit longer execution time then this type of approach is preferred. This approach is also called as 'Single PE approach'.
Fig: Serial approach
Parallel Approach (Systolic Approach):
When application demands for faster execution of code irrespective of hardware resource utilization, then this type of approach is preferred. This approach is also called as 'Systolic approach' or 'n PE approach'.
Fig: Parallel Approach
For optimization of both resource utilization and execution time and to improve area/speed metric this approach is preferred.
Fig: four PE iterative approaches