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Pulse-Width Modulation (PWM) Generation Using FPGA



Steps to perform experiment:


  1. Start simulator by clicking on the Simulation tab.

  2. Click on the link to enter the simulator.

  3. Login to your virtual Lab account.

  4. First of all select a device from Device tab.(e.g. Device->Spartan 3E)

  5. Then select an Experiment to perform from list.

  6. After filling the necessary fields click on Submit button.

  7. Here you will get answer to verify answer from simulator.

  8. Now click on Generate Verilog Code button to generate the code.

  9. Load the generated program by clicking on Load Program tab.

  10. Enter the file name without extension.

  11. Click on Save On Server button to save program on your workspace at server.

  12. Now click on Compile tab to compile your code on server.

  13. After successful compilation, click on ok to generate the test bench.

  14. Click on checkbox to select as output registers and select its type as output from list.

  15. Enter data width (MSB=7 and LSB=0 for 8-bit output register).

  16. Click on Submit button.

  17. Click on Submit Test Bench button to submit your test bench.

  18. Click on Close This Window button.

  19. Click on Execute tab which is under Compile tab.

  20. Click on Timing Analysis tab to view Timing Analysis of input program.

  21. For Resource Utilization Report click on Resource Utilizaion Report tab.

  22. Your programs are saved on your workspace at server, which you can find under Your Programs tab.

  23. If you want to write your own code Go to File-> New and repeate the procedure from step 10 to 21.



Cite this Simulator:

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